Work on power-aware physical design, floorplanning, place-and-route, signoff closure, and physical verification.
Responsibilities
- Develop power-aware physical design implementation and design-flow scripts.
- Own top-level floorplanning and automated place-and-route.
- Design and analyze power networks.
- Drive signoff timing closure, power analysis, and signal-integrity analysis.
- Run DRC and LVS physical verification.
Requirements
- Bachelor's degree or above in electronics or a related field.
- 3+ years of relevant experience.
- Familiarity with the full digital implementation flow from RTL to GDS, with strong physical design skills across placement, routing, power management, IO planning, and ECO.
- Hands-on experience with physical verification including DRC, LVS, ERC, Ant, and DFM.
- Proficiency with Tcl, Perl, Python, SDC, and STA; familiarity with synthesis, formal verification, and DFT.
Nice to have
- System PPA optimization or silicon project experience is preferred.